Dell Dimension 5150 (Pentium D) - cannot upgrade from Windows 8 to 8.1

Hi

 

I have 64-bit Windows 8 Pro (& Media Centre) installed on my Dell Dimension 5150 (Pentium D 820 running at 2.80GHz).

 

When I followed the link to upgrade to Windows 8.1 the Windows Store app opened but very quickly told me that I couldn't upgrade to 8.1!

 

For more information it opened IE and pointed to a page which highlighted the following requirements for Windows 8.1 - the processor needs to support PAE, NX and SSE2.

 

I downloaded and ran the Upgrade Assistant and it told me something different - that my processor does not support PrefetchW!

 

I would have thought that if I could install Windows 8 I should be able to upgrade to 8.1.

 

Then I found a webpage which also states that 8.1 needs the processor to support CMPXCHG16b, PrefetchW, and LAHF/SAHF.

 

Then I found CoreInfo.exe and ran it to see exactly what my CPU supports.

 

It states that it supports all six requirements (PAE, NX, SSE2, CMPXCHG16b, PrefetchW, and LAHF/SAHF).

 

I then thought that maybe I needed to enable some security feature in my BIOS (Dell version A05) but I checked that and "Execute Disable Memory Protection Technology) is enabled, so it can't be that.

 

The question is obviously: why can I not upgrade to 8.1 if my CPU supports everything that is needed? Is there a problem with the Upgrade Assistant and the Windows Store whereby it is saying I cannot upgrade? Or is there a problem with CoreInfo wrongly stating my CPU does support all the 8.1 requirements?

 

If anyone can shed some light on this I'd be very grateful.

 

Here is the output from CoreInfo:

 

Coreinfo v3.2 - Dump information on system CPU and memory topology

Copyright (C) 2008-2012 Mark Russinovich

Sysinternals - www.sysinternals.com

 

Intel(R) Pentium(R) D CPU 2.80GHz

Intel64 Family 15 Model 4 Stepping 7, GenuineIntel

HTT             *       Hyperthreading enabled

HYPERVISOR      -       Hypervisor is present

VMX             -       Supports Intel hardware-assisted virtualization

SVM             -       Supports AMD hardware-assisted virtualization

EM64T           *       Supports 64-bit mode

 

SMX             -       Supports Intel trusted execution

SKINIT          -       Supports AMD SKINIT

 

NX              *       Supports no-execute page protection

SMEP            -       Supports Supervisor Mode Execution Prevention

SMAP            -       Supports Supervisor Mode Access Prevention

PAGE1GB         -       Supports 1 GB large pages

PAE             *       Supports > 32-bit physical addresses

PAT             *       Supports Page Attribute Table

PSE             *       Supports 4 MB pages

PSE36           *       Supports > 32-bit address 4 MB pages

PGE             *       Supports global bit in page tables

SS              *       Supports bus snooping for cache operations

VME             *       Supports Virtual-8086 mode

RDWRFSGSBASE    -       Supports direct GS/FS base access

 

FPU             *       Implements i387 floating point instructions

MMX             *       Supports MMX instruction set

MMXEXT          -       Implements AMD MMX extensions

3DNOW           -       Supports 3DNow! instructions

3DNOWEXT        -       Supports 3DNow! extension instructions

SSE             *       Supports Streaming SIMD Extensions

SSE2            *       Supports Streaming SIMD Extensions 2

SSE3            *       Supports Streaming SIMD Extensions 3

SSSE3           -       Supports Supplemental SIMD Extensions 3

SSE4.1          -       Supports Streaming SIMD Extensions 4.1

SSE4.2          -       Supports Streaming SIMD Extensions 4.2

 

AES             -       Supports AES extensions

AVX             -       Supports AVX intruction extensions

FMA             -       Supports FMA extensions using YMM state

MSR             *       Implements RDMSR/WRMSR instructions

MTRR            *       Supports Memory Type Range Registers

XSAVE           -       Supports XSAVE/XRSTOR instructions

OSXSAVE         -       Supports XSETBV/XGETBV instructions

RDRAND          -       Supports RDRAND instruction

RDSEED          -       Supports RDSEED instruction

 

CMOV            *       Supports CMOVcc instruction

CLFSH           *       Supports CLFLUSH instruction

CX8             *       Supports compare and exchange 8-byte instructions

CX16            *       Supports CMPXCHG16B instruction

BMI1            -       Supports bit manipulation extensions 1

BMI2            -       Supports bit maniuplation extensions 2

ADX             -       Supports ADCX/ADOX instructions

DCA             -       Supports prefetch from memory-mapped device

F16C            -       Supports half-precision instruction

FXSR            *       Supports FXSAVE/FXSTOR instructions

FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction

MONITOR         *       Supports MONITOR and MWAIT instructions

MOVBE           -       Supports MOVBE instruction

ERMSB           -       Supports Enhanced REP MOVSB/STOSB

PCLULDQ         -       Supports PCLMULDQ instruction

POPCNT          -       Supports POPCNT instruction

SEP             *       Supports fast system call instructions

LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode

HLE             -       Supports Hardware Lock Elision instructions

RTM             -       Supports Restricted Transactional Memory instructions

 

DE              *       Supports I/O breakpoints including CR4.DE

DTES64          *       Can write history of 64-bit branch addresses

DS              *       Implements memory-resident debug buffer

DS-CPL          *       Supports Debug Store feature with CPL

PCID            -       Supports PCIDs and settable CR4.PCIDE

INVPCID         -       Supports INVPCID instruction

PDCM            -       Supports Performance Capabilities MSR

RDTSCP          -       Supports RDTSCP instruction

TSC             *       Supports RDTSC instruction

TSC-DEADLINE    -       Local APIC supports one-shot deadline timer

TSC-INVARIANT   -       TSC runs at constant rate

xTPR            *       Supports disabling task priority messages

 

EIST            -       Supports Enhanced Intel Speedstep

ACPI            *       Implements MSR for power management

TM              *       Implements thermal monitor circuitry

TM2             -       Implements Thermal Monitor 2 control

APIC            *       Implements software-accessible local APIC

x2APIC          -       Supports x2APIC

 

CNXT-ID         *       L1 data cache mode adaptive or BIOS

 

MCE             *       Supports Machine Check, INT18 and CR4.MCE

MCA             *       Implements Machine Check Architecture

PBE             *       Supports use of FERR#/PBE# pin

 

PSN             -       Implements 96-bit processor serial number

 

PREFETCHW       -       Supports PREFETCHW instruction

 

Logical to Physical Processor Map:

*-  Physical Processor 0

-*  Physical Processor 1

 

Logical Processor to Socket Map:

**  Socket 0

 

Logical Processor to NUMA Node Map:

**  NUMA Node 0

 

Logical Processor to Cache Map:

*-  Data Cache          0, Level 1,   16 KB, Assoc   8, LineSize  64

*-  Unified Cache       0, Level 2,    1 MB, Assoc   8, LineSize 128

-*  Data Cache          1, Level 1,   16 KB, Assoc   8, LineSize  64

-*  Unified Cache       1, Level 2,    1 MB, Assoc   8, LineSize 128

 

Logical Processor to Group Map:

**  Group 0

 

Regards

 

Rory

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In short, I've just found the same problem today. Interestingly, my computer is also a Pentium D based machine, a Packard Bell iMEDIA 9204.

If I understand well the following dump, my CUP doen not support PrefetchW and LAHF/SAHF. Am I rigth? Are those real prerequitises?

Thanks a lot.

Coreinfo v3.2 - Dump information on system CPU and memory topology
Copyright (C) 2008-2012 Mark Russinovich
Sysinternals - www.sysinternals.com

Intel(R) Pentium(R) D CPU 2.80GHz
Intel64 Family 15 Model 4 Stepping 4, GenuineIntel
HTT             *       Hyperthreading enabled
HYPERVISOR      -       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
EM64T           *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT

NX              *       Supports no-execute page protection
SMEP            -       Supports Supervisor Mode Execution Prevention
SMAP            -       Supports Supervisor Mode Access Prevention
PAGE1GB         -       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    -       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           -       Supports Supplemental SIMD Extensions 3
SSE4.1          -       Supports Streaming SIMD Extensions 4.1
SSE4.2          -       Supports Streaming SIMD Extensions 4.2

AES             -       Supports AES extensions
AVX             -       Supports AVX intruction extensions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           -       Supports XSAVE/XRSTOR instructions
OSXSAVE         -       Supports XSETBV/XGETBV instructions
RDRAND          -       Supports RDRAND instruction
RDSEED          -       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            -       Supports bit manipulation extensions 1
BMI2            -       Supports bit maniuplation extensions 2
ADX             -       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            -       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           -       Supports MOVBE instruction
ERMSB           -       Supports Enhanced REP MOVSB/STOSB
PCLULDQ         -       Supports PCLMULDQ instruction
POPCNT          -       Supports POPCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          *       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          -       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   -       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         *       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       -       Supports PREFETCHW instruction

Logical to Physical Processor Map:
*-  Physical Processor 0
-*  Physical Processor 1

Logical Processor to Socket Map:
**  Socket 0

Logical Processor to NUMA Node Map:
**  NUMA Node 0

Logical Processor to Cache Map:
*-  Data Cache          0, Level 1,   16 KB, Assoc   8, LineSize  64
*-  Unified Cache       0, Level 2,    1 MB, Assoc   8, LineSize 128
-*  Data Cache          1, Level 1,   16 KB, Assoc   8, LineSize  64
-*  Unified Cache       1, Level 2,    1 MB, Assoc   8, LineSize 128

Logical Processor to Group Map:
**  Group 0

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LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode
PREFETCHW       -       Supports PREFETCHW instruction

Yours DOES support those too!
So why can't we upgrade?!

Rory

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LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode
PREFETCHW       -       Supports PREFETCHW instruction

Yours DOES support those too!
So why can't we upgrade?!

Rory
I think you're misreading the CoreInfo output. I believe an asterisk (*) means "true" and a hyphen (-) means "false". So for the Pentium D 820, PREFETCHW is not supported.

I'm in the same boat with my own Pentium D 820 and it's frustrating. I have 64-bit Windows 8 installed and can't upgrade to 8.1 because of the new CPU requirements. I'm going to wait a little bit and see if Microsoft relaxes this requirement, then weigh my options if not. It seems like reinstalling 32-bit Windows 8 would sidestep this issue, but I don't want to go to the trouble if I can possibly avoid it.

Here's a related thread:

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Same here, Windows 8 Pro running fine on my P4 Prescott 3.8Ghz cpu but I get the error when trying to upgrade to 8.1 from the store.
Can't upgrade because CPU doesn't meet requirements, NX, PAE, SSE2 etc.
This is pure BS.

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I am confused by this...is don't ever recall a minor "dot 1" update changing hardware specs.   I guess if I would have known I would be shut out of upgrades I would likely have stayed with win7 on this a box.  

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From what I have read there were a number of people with the 8.1 preview who had the same issue, but a "workaround" was given.
This is truly one of the most ridiculous things ever.
Clearly my CPU is up to the task of running this OS - Microsoft needs to change this and let us upgrade.

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Seeing as support stopped at x32 Vista from Dell you wee fairly lucky to get 7 to work let alone 8.

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Thanks Chris - I think you're right, I'm misinterpreting the output!
It would have been nice if they just put "does NOT" in front of options your CPU does not support to make it a bit more obvious!

I raised this with MicroSoft Support over the phone yesterday and sent them my CoreInfo output but have heard NOTHING back from them - surprise, surprise!

I think there must be a mistake here - surely if we can install Windows 8 we should be able to upgrade to 8.1? MS can't just change hardware specs 'mid cycle' can they?!

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The fact is we WERE able to upgrade to 8 very easily so why not 8.1?!
Come MS, sort this out and let us upgrade!!

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The Pentium D 800 series does support LAHF/SAHF in 64-bit mode but there is a bug in some revisions where the processor does not report the feature in the CPUID flag.

This is from the Intel Specification Update:

As described in the IA-32 Intel® Architecture Software Developer’s Manual, support for LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors. The CPUID feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode, even though the instructions are supported and able to be executed without an Invalid Opcode exception.

The Windows 8.1 installation pre-check is undoubtedly unaware of this issue and therefore refuses to proceed.

The PrefetchW must be a red herring because it's an AMD-only instruction and, as far as I can see, it has never been supported by Intel processors.

I believe the 800 series is well capable of running 8.1 and, if we had the option of forcing the install, it should work.

In the absence of such an option it seems we have two choices if we want to run 64-bit Windows 8.1 on our old hardware: wait for Microsoft to fix the installation pre-check or replace the processor with one that doesn't have the bug. There's no guarantee that Microsoft will change anything so I have ordered the equivalent 900 series processor from eBay. These use the same socket and chipset as the 800 series and don't have the CPUID bug. It may not work with the BIOS but it was cheap enough to try. I'll post back the results once I receive it.

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Last updated June 23, 2018 Views 11,739 Applies to: